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Progress #3
Update 2007/12/13: Early release board artUpdate 2007/12/10: Added talk about fpga<->cpld clock
Posted on 2007/12/07 - 17:15
It has been a hectic few weeks with all kinds of things happening. First, we had quite a few visitors (hi!) which killed the server I was lurking on, so I had to move in no-time. Which took all night. Then at some other point Reinder fixed a new server and we could move back to the old domain but in all this moving around we confused quite a few people so now there are multiple locations people can find us. Whatever. During all that I made some changes to the website to get the layout fixed up for more browsers, so it should work in pretty much anything that's capable of displaying text. And we've got a new, more permanent domain; projectvga.org.
Besides the whole polishing of the website I received lot's of mail and comments telling me this was a cool project and refering me to other projects, help, potential issues, you name it, I received it. And it's damn motivating so keep 'em coming, I love it. I was also asked to write an article for a magazine which will be distributed to a few thousand businesses to promote my university, and in return they will cough up some of the finance needed to cover the costs of the prototype. Great! All this did push back my planned deadlines though because simply 'finishing the circuit board' suddenly became 'find a spare hour'. That makes it all somewhat annoying, knowing that you spend a week doing only organisatorial stuff without getting anything 'constructive' done. Naturally I did get stuff done, but not the stuff I was planning to. So to get that out of my system I worked a bit on some new backend stuff for perennial last week. The idea I had isn't finished yet but is shaping up quite nicely, and I'll work out the details somewhere next year or something.
Anyway, yesterday the final components (the FPGAs) arrived, so I'm finishing up the circuit board. The north side of the FPGA and the power lines of the SDRAM still have to be worked out partially, but other than that most of it is done. There are a lot of 'rough edges' however so I'll spend probably most of next week finetuning it all. To give you an idea of what I mean with mostly done, a beta screenshot:
Current progress (click for large)
And I actually believe that's all for now. I added EXT2 for any extension cards, which could use some stability after being connected to EXT1. I'll probably keep all those pins unconnected, I *might* route some to the CPLD (just in case somebody says, "I wish you'd done that, then I could've done xyz") but I'm not sure if it's possible. In any case, hang in there, the next post will be the rest of the Modules design which I'll write up sometime soon.
Update 10 dec:
This is important enough to report straight away, but not big enough to create a new entry. I received an email
from André Pouliot and after a few mails he argued:
The clock in that case would use the general
routing inside the chip before connecting to the clock tree. That would
cause a lot of timing problem for the IO on the bridge side of the chip.
In some case you could see some pin captured before or after the
transition giving you erroneous data. Also since it would be using
general routing, after each rebuild the clock would have a different
delay before arriving to the flip-flop.
You can use any pin to output a clock. For receiving it you better use a
GCLK pin. I had once to do it without using a GCLK pin I can tell you it
wasn't fun.
He has an excellent point here, so I changed the schematic in such a way that there's now a signal from the CPLD going to GCLK2 on the FPGA. I took this opportunity to make the interface to the CPLD slightly larger, so I sacrified a LED on the FPGA for this and the bus to the CPLD is now 37 lines wide, with one dedicated clock line. I'll reflect this in the other documentation later. Unfortunately, the placing of the pins on both sides makes the clock line significantly longer than the other lines. But we'll have to deal with that somehow, I can't see any other way at this point.
Update 13 dec:
Again I don't feel like writing a full entry. I gave myself the deadline of friday to get the board art finished,
and although I've got one day left I'm mostly finished. I still got to fix some details to get the ground planes
rendered nicely, which is somewhat irreversible so you don't see them here yet. Other than that, I'm good as done!
Except for a final re-check to make absolutely sure that everything is in fact, correct. For your
entertainment:
Nearly finished! (click for large)
50+ hours so far just this week. I'm completely beat. This is definitely the last time I'm routing everything by hand. Next time I'll throw more layers at it until it can route it by itself. Or let some other idiot do it. Some changes you might not instantly spot are; PCI connector is now 3.3V compatible, has holes for a bracket, and gold plating is correct. All silkscreen text is now readable and ordered. Over 600 clearance errors (mostly because I turned the minimum clearance way up above what's needed) are removed. All power lines are now thicker. A bunch of capacitors for reducing noise have been relocated. Components and wires surrounding the clocks have been reorganised to reduce any noise, as well as the power lines near the DAC. And finally, a bunch of little changes for aesthetic reasons.
[: wacco :]
Comments
Posted by WoutZoR on Fri, 07 Dec 2007 20:03:57
w00t! Looks great mate !thumbsup!
Posted by wacco on Fri, 07 Dec 2007 20:10:13
You're just trying to get a first post, aren't you?
But thanks anyway ;)
Posted by nikita on Fri, 14 Dec 2007 11:23:40
how about digital hdmi/dvi output insted of analog vga/rgb ? Who about audio ?
Posted by wacco on Sun, 16 Dec 2007 20:37:53
We looked at that and to summarise; it'd be too expensive. The serializers needed for the digital output of the DVI port would require another chip since the FPGA can't do it. HDMI is even worse, since it needs 'proprietary' black magic.
I think you mean an audio connector for HDMI? In that case, see above. If you mean audio IO in general, maybe in the near future as a separate project, although I believe there's less of a 'need' from the community for one of those because audio controllers are pretty well supported nowadays with open source drivers.
Posted by nikita on Wed, 19 Dec 2007 11:26:25
Thx.
I'm thinking about media center hdmi output ( video and audio), and yes i think is necessary another chip ( like one in OGP but for hdmi output like this http://www.siliconimage.com/iplicensing/hdmi.aspx?catid=14 ). This board will connect older systems to LCD TV with only one cable to build one nice media center. The output will be only digital.
It is not necessary to be compatible with VGA. This is my idea and is just an idea and I don't know how easy or expensive is to build.
thx again for your time.
PS: this bord can be reprogram to build older/ retro systems like zxspectrum or amiga / minimig? one usb host will be nice( opencores.org ?).
Posted by wacco on Wed, 19 Dec 2007 13:35:51
Yeah, you can use it to rebuild retro systems if you want, however minimig uses a Motorola 68000 in parallel with the FPGA, so that won't work. I think smaller systems like NES will fit without a problem.
Those silicon image chips will require some serious reworking of the circuit board if you want to include them. On an easy/expensive scale; it'll cost you the better half of a year. :)
Also, the USB connector is a device, not a host. It's used for programming the card and has a serial port connection to the FPGA, but nothing more.
Posted by nikita on Wed, 19 Dec 2007 14:07:09
thx.
I just want to know if is possible.
the cpld can include an usb host( aka controller ) and can be used with an usb stick that can hold the image of fpga. As far as I know the cpld is persistent and can be used to program the fpga. just connect the usb stick, boot and send some commands. It is possible to reprogram fpga over pci ? I know about using the usb connector to reprogram the bord.
This bord can work independent and control the computer ? (something like Wake on Lan when computer is in stand by)
how complicated is to use ddram instead of sdram
The fpga can be reprogrammed on the fly and this can be very usefull.
can you give some hints about replacing the DAC with hdmi/dvi chip ? how complicated is this operation ? How can be done ? I can't help you because I don't not how to do this, but maybe someone else will or just put the idea on todo list.
ps: just a link or two.
1.http://www.opencores.org/projects.cgi/web/tg68/overview
2.http://gamesource.groups.yahoo.com/group/minimigtg68/
3.http://www.amiga.org/modules/myalbum/photo.php?lid=3544
4.http://c64upgra.de/c-one/
Posted by wacco on Wed, 19 Dec 2007 20:52:30
I removed some of your enters, please don't enter twice when starting a new paragraph (I should really fix that in my code, but hey, I'm busy with other stuff)
Second, I guess you can connect a usb controller to the CPLD, it has plenty of IO left. However be very aware that the CPLD is *small* in programmable hardware terms so don't expect too much of it. Also, right now there's no support for 'rebooting' the FPGA without also rebooting the CPLD. This might be possible though but it wasn't on my requirements list so I haven't properly looked into it. Likewise, the JTAG bus is not accessible through PCI so you'll have to use the USB programmer. Also, the card is powered by the PCI bus so if the computer is in standby, the card won't work at all.
I think DDR SDRAM is possible. Same goes for connecting a DVI chip. All you have to do is find a chip you want to use, read it's datasheet, and connect the proper lines to the FPGA. As you can see, I'm having 3x 8 bits, plus a clock and some sync lines going from the FPGA to the DAC. You'd have to do something similar for a DVI chip. If you want something like this, I suggest you start your own project!
The tg68 project is really nice, I hadn't heard of that yet. If it fits (including the rest of minimig) on a xc3s400, then yes, minimig will probably run on this card.
Posted by wacco on Wed, 19 Dec 2007 21:37:23
Never mind about the enters, fixed them.
Posted by louis vuitton on Tue, 15 Jun 2010 12:21:05
see, I'm having 3x 8 bits, plus a clock and some sync lines going from the FPGA to the DAC. You'd have to do something similar for a DVI chip. If you want something like this, I suggest you start your own project!
The tg68 project is really nice, I hadn't heard of that yet. If it fits (including the rest of minimig) on a xc3s400, then yes, minimig will probably run on this card.
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